Multicarrier Faster-than-Nyquist Signaling Transceivers: From Theory to Practice

The demand for spectrum resources in cellular systems worldwide has seen a tremendous escalation in the recent past. The mobile phones of today are capable of being cameras taking pictures and videos, able to browse the Internet, do video calling and much more than an yesteryear computer. Due to the variety and the amount of information that is being transmitted the demand for spectrum resources is continuously increasing. Efficient use of bandwidth resources has hence become a key parameter in the design and realization of wireless communication systems. Faster-than-Nyquist (FTN) signaling is one such technique that achieves bandwidth efficiency by making better use of the available spectrum resources at the expense of higher processing complexity in the transceiver. This thesis addresses the challenges and design trade offs arising during the hardware realization of Faster-than-Nyquist signaling transceivers. The FTN system has been evaluated for its achievable performance compared to the processing overhead in the transmitter and the receiver. Coexistence with OFDM systems, a more popular multicarrier scheme in existing and upcoming wireless standards, has been considered by designing FTN specific processing blocks as add-ons to the conventional transceiver chain. A multicarrier system capable of operating under both orthogonal and FTN signaling has been developed. The performance of the receiver was evaluated for AWGN and fading channels. The FTN system was able to achieve 2x improvement in bandwidth usage with similar performance as that of an OFDM system. The extra processing in the receiver was in terms of an iterative decoder for the decoding of FTN modulated signals. An efficient hardware architecture for the iterative decoder reusing the FTN specific processing blocks and realize different functionality has been designed. An ASIC implementation of this decoder was implemented in a 65nm CMOS technology and the implemented chip has been successfully verified for its functionality

Low latency communication over commercially available LTE and remote driving

In addition to autonomous car operation, in many cases it is desirable to let a human drive the vehicle remotely. To make remote operation possible, it is very critical to have a low and predictable latency to transmit video from the car cameras and receive control commands back. In this paper, we analyze the problem and present a communication and video streaming system that addresses the latency challenges and enables teleoperation of a real car over commercially available LTE network; demonstrating sub-50ms roundtrip latencies for 720p, 60FPS video, with average PSNR 36db

A generic hardware MAC for wireless personal area network platforms

This paper presents a generic hardware-MAC for systems designed based on high rate (IEEE 802.15.3) and low rate (IEEE 802.15.4)Wireless Personal Area Networks. functionality that are better run in hardware are moved over from the software part of the MAC layer. An easy to access memory like interface has been defined for data and control transfer between the software and hardware parts of theMAC layer. A key challenge in designing such a system was to arrive at a generic architecture without compromising with either of the standards on the lines of which the two systems are implemented. Emphasis on reuse of the modules has been done in order to avoid repetition of design and implementation effort and in turn reducing the time required for testing. The design has been successfully tested on different FPGA platforms

Coprocessor accelerated OpenMAX MP3 decoder

This thesis evaluates the feasibility of designing a coprocessor to accelerate multimedia functions in the OpenMAX standard. OpenMAX is a new standard from the Khronos group, a member funded industry consortium, to integrate the most popular multimedia functions like MP3, MPEG-4 and H.264 under one roof. It provides royalty-free API that helps in developing and/or accelerating the specified standards on a wide variety of platforms and devices. The MP3 subsection in OpenMAX was implemented for evaluating the standard. A high level simulation model of the system consists of a processor core, cache, memory and coprocessor. The coprocessor provides instruction set extensions for the CPU to accelerate the intended functions and was modeled using SystemC like language. The result is evaluated in terms of the speedup obtained. The MP3 decoding process was accelerated 1.2 times as a result of accelerating the DCT by 4 times. The simulations further established the importance of avoiding memory access bottlenecks. The silicon area of the coprocessor was estimated to be half of the original specification limit

Complexity analysis of IOTA filter architectures in Faster-than-Nyquist multicarrier systems

This paper has evaluated the overhead requirements for IOTA pulse shaping filters employed in faster-than-Nyquist multicarrier systems. Faster-than-Nyquist signaling has shown the promise of improving bandwidth efficiency, but comes at the cost of increased processing complexity in the transceiver. The IOTA filter being one of the blocks contributing for the processing overhead, different architectural options have been evaluated. A comparison is drawn between the architectures of the IOTA filter and the suitable architecture with moderate hardware overhead is chosen for implementation

Hardware architecture of IOTA pulse shaping filters for multicarrier systems

This paper presents a hardware architecture of pulse shaping filter used in multicarrier systems. The filter can be configured to be used for both transmitter and receiver with limited overhead. Generic implementation complexity analysis for a filter in a multicarrier system with N sub-carriers is presented, while the implemented architecture is for a system with 128 sub-carriers. The pulse shaping filter is part of a larger system based on faster-than-Nyquist signaling and aided in an overall complexity reduction. Hence designing an efficient hardware architecture to keep the overhead moderate was the motivation behind this work. Architectural optimizations has been carried out in order to reduce area and power. The implementation of the proposed hardware architecture was carried out using a 65nm CMOS process. The chip core occupies an area of 0.11mm2 and is estimated to consume 14.4mW of power when running at 200MHz

Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder

Architectural improvements for a multicarrier faster-than-Nyquist (FTN) decoder are presented in this work. A previously designed FTN decoder has been optimized during implementation, especially with respect to memory considerations to reduce area and power. The memory optimized architecture achieves 28.7% savings in overall chip area and provides 43.8% savings in the estimated power compared to the pre-optimized design. The BER performance tradeoff from one of the memory optimization shows that the degradation is acceptable and can actually provide better performance for certain scenarios. The other memory optimization considers the minimal buffering required within the interference canceller, resulting in memory reduction close to 50% of what was previously reported. The performance from the actual RTL implementation of the FTN decoder is also presented in comparison with the floating and fixed point benchmark performances

Multicarrier faster-than-Nyquist transceivers: hardware architecture and performance analysis

This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of FFTs for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time-frequency spacing, finite wordlengths and their design trade-offs for reduced complexity iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65nm CMOS and FPGA. From the hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead

An 0.8-mm(2) 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS

This paper presents an iterative decoder for faster-than-Nyquist (FTN) and orthogonal signaling multi-carrier systems. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65-nm CMOS process and occupies a total area of 0.8 mm(2) with decoder core taking up 0.567 mm(2). The power consumption of the chip is 9.6 mW at 1.2 V when clocked at 100 MHz, providing a peak information throughput of 1 Mbps and with an energy efficiency of 0.6 nJ per bit per iteration. To the best of our knowledge, those measurement results are from the first ever silicon implementation of a decoder for FTN signaling